1. Field of the Invention
This invention relates to methods of precisely forming through holes in (100) silicon wafers by orientation dependent etching (ODE) either before or after fabrication of the integrated circuit on the wafer. More specifically, the invention involves ODE to fabricate integrated circuit (IC) wafer subunits having precision through holes which define butt edges or surfaces for forming a butted array of subunits. The ability to precisely locate and dimension butt edges or surfaces of IC wafer subunits (or chips) finds use in the precision delineation of these wafer subunits for any extended array using subunit modules. Wafer subunits are aligned in extended arrays to form, e.g., pagewidth printheads for inkjet type printers, or RIS and ROS arrays.
2. Description of Related Art
Previous attempts at placing through holes in silicon wafers after integrated circuit fabrication have encountered many problems. Since virtually all integrated circuit fabrication is done in (100) silicon wafers, the most precise fabrication process involves etching (111) plane troughs or recesses into a surface of the wafer. However, it was impossible to apply the standard etch resistant masking layer of pyrolytic silicon nitride over the integrated circuitry due to the high temperature (greater than 800.degree. C.) process for that film, which would cause silicon-aluminum interdiffusion. Consequently, one previous method for fabricating through holes involved etching (111) plane troughs into a back surface of a wafer opposite the upper circuit surface so that the troughs would just intersect the upper surface of the wafer. A fundamental problem with etching only through the back surface of the wafer is that the width of the opening on the unetched upper surface is a function of the wafer thickness Since it is not uncommon for wafers to have variations in thickness, it has not been possible to precisely locate openings on the circuit side of the wafer. For example, if the etch mask is designed to produce a through hole H adjacent the integrated circuit IC and just reaching the upper integrated circuit surface CS of a 20 mil thick wafer W.sub.1 (see FIG. 1B), it will actually produce a 1.4 mil wide opening on a 19 mil thick wafer W.sub.2 (FIG. 1A) and will not produce any opening at all on a 21 mil thick wafer W.sub.3 (FIG. 1C).
The effect of variations in wafer thickness is addressed in U.S. Pat. No. 4,169,008 to Kurth, the disclosure of which is herein incorporated by reference. Kurth discloses a method of forming an ink jet nozzle in a (100) silicon wafer by etching through obverse and reverse surfaces of the wafer. The method does not produce butt edges and is not performed after integration circuit fabrication on the wafer. The etch resistant layer used by Kurth '008 is not plasma silicon nitride.
Thermal ink jet printers contain printheads, such as roofshooter printheads shown in FIG. 2 and described in U.S. Pat. No. 4,789,425 to Drake et al (the disclosure of which is herein incorporated by reference). The printheads are constructed from silicon wafer subunits (or chips) 1 which include nozzles 2, reservoirs 3 for conducting ink to the nozzle outlets and integrated circuitry 4. The integrated circuitry includes a resistive heater element which responds to an electrical impulse to vaporize a portion of the ink in a passageway 6 which provides the motive force to form an ink drop which is expelled onto a recording medium. Some printheads, such as sideshooter printheads shown in FIG. 3 and described in U.S. Pat. No. 4,601,777 to Hawkins et al (the disclosure of which is herein incorporated by reference), are formed from a number of wafer subunits S.sub.1, S.sub.2, S.sub.3 butted together and layered upon a support substrate. The sideshooter printhead includes nozzles 7 and resistive heater element circuitry 8 located on a heater substrate 9 for controlling ink output from each nozzle 7. In each case, the printhead is wired to a daughter board, placed in communication with a source of ink and mounted on a carriage of an ink jet printer for reciprocation across the surface of a recording medium, such as paper. Alternatively, a pagewidth array of wafer subunits, as shown in FIG. 4, can be formed by butting together a plurality of subunits S.sub.1, S.sub.2, S.sub.3 into the length of a pagewidth. In a pagewidth array configuration, the array is fixed and the recording medium moves at a constant velocity in a direction perpendicular to the array.
Since silicon wafers are not currently available having a length corresponding to a pagewidth, the current practice is to form the nozzles, passageways and integrated circuitry on silicon wafers, separate these wafers into wafer subunits (or chips) which contain butt surfaces or edges, align these subunits along their butt surfaces or edges into an array having a length of a pagewidth, and attach the array to a substrate to form a pagewidth printhead. The layering of the wafers, if necessary, to form the complete printhead can be performed before or after separation into subunits. Since many wafer subunits are aligned to form an array, each subunit must be uniform. In order for the subunits to be uniform, the location of the butt edges or surfaces relative to the circuitry must be precise. Additionally, since the step of separating a wafer into subunits is performed as a batch, well prior to the step of aligning the subunits into arrays, the later step usually involves selecting subunits from a bin which contains subunits having a variety of thicknesses. When the subunits S.sub.1, S.sub.2 are formed with diagonal butt surfaces, a difference in height .DELTA.h between adjacent subunits results in a lateral shift 0.7 .DELTA.h of the circuit surfaces CS of these subunits (see FIG. 5).
One previous technique for forming butt edges, shown in FIGS. 6A-6B, involves orientation dependent etching a groove 10 on one surface of the wafer, placing a dice cut 11 in the opposite surface of the wafer and applying a force F to fracture break the wafer along line 12 into subunits to produce butt edges 13. Adjacent subunits are then butted together at the butt edges 13 (FIG. 6B). Disadvantages of this technique are: the fracture edges can produce cracked passivation up to 50 micrometers away, the butt edges 13 are razor edges which are easily damaged, and any difference in chip thickness .DELTA.h between two subunits results in a lateral shift of 0.7 .DELTA.h of one chip surface relative to the other. This lateral shift is due to the angle of the (111) etched surfaces.
Another previous method for forming butt surfaces, illustrated in FIG. 3, involves orientation dependent etching troughs entirely through the wafer, giving a parallelogram cross section to the wafer. By this method, the butt surfaces 15, 16 are crystal (111) planes. Advantages of this method are (1) the butt surfaces are formed gently by wet etching, and (2) the butt surface is a robust crystal plane. A disadvantage is that two separate through etches are required and the area between the butted surfaces is so large that dirt particles can prevent intimate butting.
Another previous method, illustrated in FIGS. 7A and 7B, which requires only one through etch, involves making at least one through etch 20 on one surface of the wafer to define a first butt edge 21 and dividing the wafer into DIE 1 and DIE 2, forming a trough 22 on the other surface of the wafer, and then making a dice cut 23 through the trough 22 to form a second butt edge 24. The first butt edge 21 of each subunit is butted against the second butt edge 24 of an adjacent subunit (FIG. 7B) to form the array. This method reduces the amount of etch time required and also reduces the butt edge area. However since a dice cut is required, it is possible to produce cracked passivation. This method also is susceptable to a lateral displacement of 0.7 .DELTA.h due to differences in adjacent chip height .DELTA.h.
A further previous method, illustrated in FIGS. 8A and 8B, involves producing butt edges by reactive ion etching (RIE) from the circuit surface to a groove G cut into the base surface. This method is advantageous in that it produces vertical butt surfaces 25, 26 and thus differences in the height of adjacent butting chips do not result in lateral displacements. A disadvantage is that the RIE trenches must be etched prior to metal oxide silicon (MOS) fabrication due to potential oxide damage from the high energy ions.
U.S. Pat. No. 4,601,777 to Hawkins et al discloses thermal ink jet printheads which are formed in (100) silicon wafers. The wafers can be separated into subunits to form printheads and the printheads can be aligned into pagewidth arrays. The wafers are separated into printheads by dicing.
U.S. Pat. No. 4,612,554 to Poleshuk discloses a thermal ink jet printhead and method of making same. The printheads are formed from (100) silicon wafers on which the integrated circuits are fabricated after application of an etch resistant pyrolytic silicon nitride layer. Poleshuk discloses dicing to form butt edges.
U.S. Pat. No. 4,784,721 to Holmen et al discloses a process for fabricating a thin film microsensor for airflow. The process only etches through a back surface of a (100) silicon wafer, does not provide a through hole in the wafer and does not discuss the fabrication of butt edges.